Working Through CMOS Digital Design Without Losing Your Mind
The Kang textbook covers a lot of ground, and honestly most people buy it expecting a straightforward guide to CMOS logic gates and end up confused why simulation results don't match hand calculations. I ran into this exact issue back when I was designing a custom clock divider for a sensor interface. The textbook assumes ideal conditions, which is fine for learning but doesn't prepare you for what happens when you actually run the circuit in a foundry tool. The full title is CMOS Digital Integrated Circuits: Analysis and Design by Sung-Mo Kang and Yusuf Leblebici. It is primarily used as a graduate-level textbook, though many practicing engineers reference it when they need to revisit sizing equations or understand the transition from NMOS to CMOS and why that shift actually mattered for power dissipation. The book covers static CMOS gates, noise margins, delay models, pass transistor logic, CPL, domino logic, and then moves into more advanced topics like CMOS latch design and VLSI interconnect. What the book does well is its treatment of the Elmore delay model and the method of logical effort, which is the framework used throughout to estimate propagation delay through a logic chain. That part is genuinely useful. The derivations for the parasitic capacitances, the input capacitance contributions from diffusion areas, and the way gate sizing scales with fanout are all laid out clearly enough that you can use them directly in a design flow.
What it does not cover well is the reality of design rule checking and layout parasitics. I designed a four-stage inverter chain to drive a large capacitive load, sized everything according to the textbook equations, and when I ran the SPICE extraction the delay was nearly double what I predicted. The problem was parasitic coupling between adjacent metal lines on the top routing layer that the textbook never discusses. I ended up adding shielding around the critical signal nets and recalculating the effective fanout with the extracted parasitic capacitances included. That process took about six hours that could have been cut down significantly if I had accounted for coupling capacitance during the initial sizing phase instead of treating it as a post-layout fix. Another thing beginners consistently miss is the treatment of short-circuit power. The book presents the formula and explains the condition under which both the PMOS and NMOS conduct simultaneously, but it does not emphasize enough that this effect scales with rise and fall time, not just load capacitance. In practice I found that using asymmetric slew control on a medium-complexity gate reduced short-circuit power by roughly 30 percent without changing the silicon area. The textbook mentions this but buries it in a later chapter, so people tend to overlook it until their power budget is already exceeded. The section on dynamic and domino logic is probably the strongest part of the book. The explanation of precharge and evaluation phases, the race condition risks, and the need for footer transistors on domino gates are all explained with enough detail that you could actually design a circuit from that chapter. I once reviewed a student layout that had a domino OR gate with no keepers and it failed during functional verification because of charge sharing between internal nodes. Adding a weak PMOS keeper, as the book describes, fixed it in under ten minutes. That is the kind of practical detail that matters more than the theoretical derivations.
The pass transistor logic chapter is useful but limited. If you are only working with standard cell designs in a modern process, you will rarely see bare transmission gates in a final floorplan. The textbook's treatment is still valuable for understanding how to minimize transistor count in specific functions like XOR and multiplexers, but it does not address threshold voltage degradation in long chains of pass transistors, which is a real problem in older processes and still relevant when you are working with custom analog switches in mixed-signal designs. One thing the book gets wrong by omission is the treatment of leakage currents. Modern CMOS processes have subthreshold leakage and gate leakage that dominate power in deep submicron designs, and this textbook was written before those effects became primary concerns. If you are using it as a reference for a current process node, you need to supplement it with papers or manuals that cover multi-Vt strategies and power gating. The core analysis remains valid, but the power numbers you will calculate from the book alone will be off by an order of magnitude in a contemporary node. The problems at the end of each chapter are still the best part of this book for building intuition. They are not trivial. I would suggest doing at least the first problem in each chapter by hand before looking at any solution manual, because the exercise itself forces you to engage with the equations in a way that passive reading does not. A typical problem on gate delay optimization takes about twenty minutes, and doing five of them per week over a semester is enough to build solid design instincts.
Get the Full Details
If you are looking for a PDF or download link, I do not have one and should not provide one. The book is published by McGraw-Hill and is available through standard academic channels. What I can tell you is that the third edition is the most complete version and includes more coverage of low-power design than earlier editions. If you find yourself constantly referencing one chapter, it is usually the delay optimization or domino logic sections, which means you should re-read those with a focus on the problem sets rather than skimming the derivations. There are better books for specific subtopics. Rabaey covers layout and interconnect more thoroughly. Weste and Harris has more on physical design. But for a single-volume reference that gets you from device physics through sequential circuit design, Kang is still one of the most practical options available. Just do not treat it as a complete design manual. It is a foundation, not a finish line.
