Getting an NMOS Transistor Built Right
NMOS fabrication is mostly about getting layers in the right place with the right doping concentrations. The basic process runs through substrate preparation, well definition, gate stack formation, source/drain implantation, and metallization. That's the textbook version. The real world is messier. Most fabs still use a p-type silicon substrate for NMOS devices since the channel forms at the silicon-oxide interface when you apply a positive gate voltage. You grow a thin gate oxide thermally — usually in a wet or dry oxidation furnace at around 800-1000°C. The oxide thickness directly controls your threshold voltage, so you're talking sub-20 nanometer ranges for modern devices. A 10nm oxide grown dry gives you roughly 2.5-3V Vt on a typical substrate, but the exact number depends on dopant concentration underneath. You measure this with C-V testing after the fact because you can't reliably predict it from the furnace cycle alone.
Fabrication Process Nmos Making
After the gate oxide, you deposit polysilicon through LPCVD at around 600-650°C. This polysilicon gets doped with phosphorus or arsenic while it's growing to keep resistance low. Then you pattern it using photolithography and etch it — typically a reactive ion etch with a chlorine-based chemistry. The polysilicon gate acts as your mask for the source and drain implants, which is why gate alignment tolerance matters so much during the lithography step. The source and drain are formed through ion implantation, usually arsenic for NMOS because it has less channeling than boron. You tilt the wafer 7 degrees during implant to avoid channeling effects through the crystal lattice. Before the main implant, you often do a lighter LDD (lightly doped drain) implant at lower energy to reduce hot carrier effects. The main source/drain implant follows at higher energy and dose — maybe 15-30 keV and 1-5 x 10^15/cm² depending on what you're building. After implantation comes annealing. Rapid thermal annealing at 900-1050°C for 10-30 seconds repairs the crystal damage from implantation and activates the dopants. This step is critical. If you under-anneal, you get high contact resistance and unreliable devices. Over-anneal and the dopants diffuse too far laterally, shrinking your effective channel length and shifting your threshold voltage. You want around 0.1-0.2 microns of lateral diffusion for a 0.18µm process node, give or take.
Next you deposit an interlayer dielectric — typically silicon dioxide or a low-k material — using PECVD. You etch contacts down to the source, drain, and gate regions. Metal deposition follows, usually aluminum-copper alloy or copper depending on the technology node, then you pattern the metal layer through lithography and etching. Passivation covers everything at the end to protect against moisture and contamination. One thing most guides don't mention: the silicide step. Before you deposit the interlayer dielectric, you often form a silicide on the polysilicon gate and the exposed source/drain regions to reduce sheet resistance. Titanium silicide or cobalt silicide gets reacted onto those surfaces at 500-600°C, then you strip the unreacted metal with a selective etch. Skip this and your contact resistance will dominate your on-resistance, especially at smaller geometries. I ran into a problem once where my threshold voltages were drifting by over 0.5V between wafers in the same batch. Turned out the oxide growth furnace had a slightly uneven temperature profile across the wafer tray position. Wafers near the edges grew thicker oxide by about 1.5nm compared to center positions. Since Vt scales inversely with oxide capacitance, that thickness variation translated directly into Vt spread. The workaround was swapping my process recipe to grow the gate oxide using a different furnace slot that had better thermal uniformity, and implementing a pre-oxidation clean with a short HF dip to remove any native oxide that had rebuilt before loading. After that, Vt variation dropped to under 30mV across the wafer.
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Another thing to watch: spacer formation. After the gate is defined, you deposit a thin sidewall spacer — usually silicon nitride or oxide — and anisotropically etch it back. These spacers serve multiple purposes. They define the self-aligned source/drain implant boundaries, they help isolate the gate from the source and drain contacts, and they reduce parasitic capacitance. If your etch recipe eats into the gate oxide underneath the spacer, you've created a leakage path that won't show up in continuity tests but will kill your subthreshold swing. Test this with IV characterization early, not after you've built a whole circuit. Channel doping is another area where people cut corners. A light channel dopant through the wafer or a localized channel stop implant sets your base threshold voltage. Too light and you get excessive DIBL (drain-induced barrier lowering) in short-channel devices. Too heavy and your mobility drops because of increased phonon scattering. Typical values sit around 1-5 x 10^12/cm² for surface channel dose, but this really depends on your target Vt and channel length. For anything below 0.35µm, you need to model this with a TCAD simulator before committing to a process flow. The backside of NMOS fabrication — things like substrate contact formation and well tie structures — gets glossed over in most documentation but matters for latch-up immunity and noise coupling. If you're building analog circuits, substrate noise from digital switching can couple directly into your sensitive nodes through the silicon. A guard ring of p+ implants around your analog devices, tied to the lowest potential, will shunt most of that away. Cost you two extra masks and maybe an hour of fab time, but it prevents debugging sessions that last weeks.
Process integration is where things get expensive. Every mask layer adds cost. A basic discrete NMOS needs maybe 8-12 masks. A CMOS process with both NMOS and PMOS runs 20-30 masks minimum. Each mask reticle costs thousands of dollars, and alignment errors compound as you add layers. If you're doing research or low-volume work, look into multi-project wafer (MPW) services where several designs share a single mask set. You sacrifice some layout freedom but cut costs by 90% or more compared to a full custom run. For learning purposes, some universities and research labs offer foundry access through shuttle programs. TSMC, GlobalFoundries, and a few academic fabs like IMEC have educational programs. You submit your GDSII layout and they include it in a shared tapeout. Turnaround is typically 6-12 weeks. The designs are limited to their available process design kit rules, so you can't push geometry beyond their minimum, but it's real silicon and real processing, not a simulation. If you're designing for volume production, process design kits from commercial foundries include parametric test structures built into your layout. These include array test patterns for checking alignment, etch rates, and electrical parameters without consuming significant die area. Don't skip the test structures. You'll waste more time characterizing a bare transistor than you'll save by omitting them.
One final note on reliability: electromigration becomes a real concern in NMOS source and drain connections at high current densities. Aluminum tracks fail around 10^6 A/cm², while copper handles roughly 3-5 x 10^6 A/cm² before showing signs of degradation. If your design routes high current through narrow metal traces, upsize the width or switch metal layers. You can calculate this yourself with the standard Black's equation for MTBF, but a practical rule of thumb is keeping current density below 50% of the rated limit for long-term reliability.
