Simulating PLLs Without Crying Later
Most engineers treat PLL simulation as a checkbox exercise. They run a transient analysis, check lock time, call it done, and then wonder why their board noise is 20dB above spec. I've spent enough nights re-spinning boards because someone skipped the right simulation steps that I can tell you exactly where the process breaks down. The core of PLL simulation isn't the lock detection. It's modeling the phase detector, charge pump, loop filter, and VCO with enough parasitic detail that the simulation actually matches silicon. A clean simulation uses a behavioral VCO model with phase noise sourced from measured data, not a generic SPICE VCO. The loop filter needs ESR and capacitor parasitics included. The charge pump has leakage current and current mismatch that will kill your in-band phase noise if you ignore them. I used to build these simulations in Spectre. Now I use ADS with Virtuoso co-simulation, and the difference is roughly six hours of debug time saved per project. The tradeoff is setup complexity. Getting the boundary between behavioral and transistor-level models right takes patience, but once it's working, it runs every iteration after that.
Here's the part most designers get wrong. You need two separate simulation passes. First is the transient lock acquisition run, which can take minutes or hours depending on your reference frequency and division ratio. Second is the phase noise walkover, which sweeps simulation parameters like loop bandwidth and VCO tuning voltage across a range. If you combine these into one run, you're looking at simulation times that make your timeline unrealistic. I separate them. The transient gets a shorter window—just enough to confirm lock. Then I freeze the operating point and run the noise analysis. One thing that will bite you: the phase detector gain Kpd varies with input amplitude and supply voltage. Most tutorials treat it as a constant. It isn't. In my experience with a 5GHz integer-N PLL design, I saw 15% variation in Kpd across the specified voltage range, which shifted the loop bandwidth by about 800kHz. That 800kHz moved the VCO phase noise foldover point into a region where the reference spurs were already borderline. The fix was simulating Kpd across multiple PVT corners and using the worst case for loop filter design, not the nominal value. I added a Monte Carlo sweep on the charge pump current and found that 1% current mismatch produced spur levels 12dB higher than the matched simulation predicted. Another counter-intuitive thing: wider loop bandwidth isn't always better for jitter. For a given VCO, narrowing the loop bandwidth lets more high-frequency VCO phase noise through, which increases integrated jitter. But widening it pulls in more reference and charge pump noise from the in-band region. The optimum is usually where the in-band noise floor meets the VCO noise floor, and that point shifts with component aging and temperature. I run corner simulations at 40C, 25C, and 125C. The loop bandwidth that gives minimum jitter at 25C might not be the same at the extremes.
Simulink is another option, especially if you're doing system-level co-design. It's faster for iterating on architecture choices like divide ratios and modulation schemes. But it won't catch second-order effects like substrate coupling or supply noise interactions. I use it early for top-level parameter selection, then move to circuit-level simulation for final verification. The simulation tools themselves have quirks. In ADS, the PLL Demodulator block is useful for spectrum analysis but it assumes an ideal frequency detector. If your actual implementation uses a digital phase-frequency detector with dead zone effects, the simulation won't show the spurs that come from that. You need to model the dead zone explicitly or inject a test pattern that reveals it. In Cadence, the PSS/PSS-noise analysis is powerful but finicky. Convergence issues are common when your loop filter has high-Q poles near the loop bandwidth. I usually add a small series resistance to the loop filter capacitors to damp the resonance and help convergence. It's a non-physical tweak for simulation purposes, but it doesn't affect the final results meaningfully. If your PLL is for a application with tight spectral mask requirements, you need to simulate spurs at offsets from 10kHz to 10MHz minimum. A common mistake is only checking the spur at the reference frequency offset. The spurs at sub-harmonic offsets can accumulate and push your noise floor up in a way that hurts EVM more than the single-tone spur measurement suggests. I simulate with a realistic modulated signal, not just a CW tone, because the dynamic behavior of the VCO tuning port under modulation affects loop stability in ways a static analysis won't show.
Get the Full Details
Sometimes simulation simply cannot replace hardware. If your VCO uses an LC tank with a custom inductor, the Q factor and parasitic coupling to the substrate are difficult to model accurately without EM extraction. I run the PLL simulation with worst-case Q values from EM analysis. If the simulation margin is thin, I don't trust it. I build a test chip with programmable loop filter components so I can tune the bandwidth post-fabrication. That adds about 15% to the mask cost but saves weeks of re-spin time when the simulated and measured performance diverge. For initial exploration, there's also the SyntheSpect tool from Analog Devices if you're working with their PLL devices, and Texas Instruments has a PLL Synthesizer Design Tool. These are good for quick parameter estimation but limited in their ability to model non-ideal behavior. They're useful for getting ballpark numbers, not for final verification. ADIsimPLL is probably the most capable free tool for this kind of work if you're designing with ADI parts. It handles fractional-N synthesis, spur analysis, and jitter budgeting. The interface is dated but the underlying math is sound. I use it alongside circuit-level simulation to cross-check results. When the two disagree, I trust the circuit simulation, because ADIsimPLL uses simplified noise models.
The most important habit is saving your simulation cases with clear naming conventions. A PLL simulation project generates dozens of variations. Without organization, you'll spend more time finding the right .sps file than you will running the next iteration. I use a naming scheme that encodes the PVT corner, loop bandwidth, and simulation type. It takes two extra minutes per case but saves me two hours per project when I need to compare results.
