What SAR ADCs Actually Do
A Successive Approximation Analog To Digital Converter works by guessing the input voltage bit by bit, starting with the most significant. It has a DAC inside, a comparator, and a control register that does the actual approximating. The core loop is simple: set a bit, see if the DAC output is above or below the input, keep it or drop it, move to the next bit. That is it. Done in a fixed number of cycles equal to the resolution. An 12-bit converter takes 12 clock cycles plus a few for setup and readout. You get a deterministic latency. Nothing fancy about the theory. What people don't always realize is that the SAR architecture is actually one of the most flexible ADC types out there. You can do differential inputs, you can do pseudo-differential, you can chop, you can do calibration, you can run it at very low power because it doesn't need a continuous oscillating chain like a sigma-delta or a whole parallel bank of comparators like a flash. That flexibility is why you see them everywhere from microcontroller peripheral blocks to precision measurement rigs. But flexibility also means you can shoot yourself in the foot if you treat it like a magic black box.
Successive Approximation Analog To Digital Converter Design
Let me walk through what matters when you are actually selecting and using one. The first thing to check is your reference voltage. A lot of engineers pick an ADC because the resolution looks good on paper, then realize the reference is noisy or has too much temperature drift. The code you read from the converter is directly proportional to Vref. If Vref moves, your measurement moves with it. Period. A low-noise LDO feeding the reference pin, or better yet a dedicated voltage reference part, will save you more headaches than almost anything else you can do. The sampling capacitor is another thing that bites people. Inside every SAR ADC there is a tiny sampling capacitor that gets charged up when the converter starts a conversion. If your source impedance is too high, that capacitor doesn't fully settle before the next step. You get gain error, nonlinearity, or just plain wrong readings. Most datasheets will tell you the maximum source impedance, usually somewhere in the range of a few hundred ohms to a couple of kiloohms depending on the part. If you are driving it from a high-impedance sensor or a voltage divider, you need a buffer op-amp. Don't skip it because the schematic looks cleaner without one. I ran into a case where a design used a SAR ADC to monitor battery voltage through a 100k + 10k resistor divider. The datasheet said max source impedance was 10k. I ignored it because the converter was only updating once per second and I thought that would be fine. It wasn't. The readings were consistently off by about 3 percent, and the error got worse as the battery voltage dropped. What was actually happening is that at lower voltages the internal sampling capacitor took longer to charge through that high resistance, and the conversion was finishing before full settling. I added a simple rail-to-rail op-amp buffer between the divider and the ADC input. Error dropped to under 0.1 percent. That was the only fix that mattered.
Real Timing Behavior
One thing that trips people up is the timing between the Start-of-Conversion pulse and when the data is actually ready. Some SAR ADCs have an internal watchdog timer that truncates conversions if they run too long. If you are operating at high temperature or with an unusually slow reference, you might find the converter occasionally returns garbage codes. The workaround is usually to check the status pin or poll the ready line instead of blindly assuming a fixed delay after the start pulse. I learned this the hard way on a project running at 85C ambient. The converter was fine at room temperature and failing intermittently in the field. Tracing it down took about two days because the symptoms looked like a software bug rather than a timing issue. The clock input is another area where beginners make mistakes. Some SAR ADCs have an internal clock divider. Some don't. If the part requires an external clock, you need to make sure the clock duty cycle is reasonable and the edges are clean. A sloppy clock with slow rise times can cause the successive approximation logic to miss a bit decision, which introduces non-monotonic codes or missing codes. I had a board where the clock trace was running right next to a switching regulator node. The SAR was picking up noise on the clock line and producing spurious codes that looked like random jumps in the measurement. Moving the clock trace to an inner layer with a solid ground reference and adding a small series resistor near the ADC clock pin fixed it. Not the most elegant solution but it worked.
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Noise and Filtering
SAR ADCs are not immune to noise, and unlike sigma-delta converters they don't do oversampling and noise shaping inherently. You need to handle your own noise filtering. That means putting a small RC filter on the analog input if your application allows the tradeoff in bandwidth. A 1k resistor and 100nF capacitor gives you about 1.6kHz of bandwidth, which is plenty for most DC or slow-moving signals and does a decent job of rejecting high-frequency noise. But be careful: adding too much capacitance on the input can load down your buffer or the source and reintroduce the settling problem I mentioned earlier. There is a balance here that you have to figure out for your specific circuit. Digital noise from the ADC itself can couple back into the analog section. SAR converters switch large capacitor arrays internally during each bit decision. Those switching currents flow through the ground and power pins and can create voltage spikes. If your ground plane isn't solid or your decoupling is weak, those spikes show up as noise on your measurements. Two things help: a proper ground plane and a ceramic capacitor close to each power pin on the ADC. I'd recommend 0.1uF minimum, and if the datasheet specifies a larger value for the reference bypass, use that too. Don't skimp on the bypass capacitors. They are cheap and they matter.
Calibration and Linearity
Most SAR ADCs have integral nonlinearity specs that are good enough for general-purpose use. But if you need better than the datasheet guarantees, you can do a two-point calibration at room temperature and it usually shaves off half the error. Apply a known low voltage and a known high voltage, measure the codes, compute a scale factor and offset, and apply it in software. For a 12-bit part this can easily cut ENOB loss from 0.5 LSB down to 0.2 LSB or better. It is a small amount of work for a meaningful improvement. Temperature is the enemy of accuracy in SAR converters. The internal reference, the DAC capacitor array, and the comparator all shift with temperature. If your application spans a wide temperature range, a single-point calibration won't cut it. Some parts offer internal temperature-compensated references or even on-chip calibration registers that you can update periodically. Check the datasheet for that. If the part doesn't have it, you are looking at either a burn-in calibration at multiple temperatures or accepting whatever drift comes with the device. There is no free lunch here.
When SAR Is the Wrong Choice
I should mention that SAR ADCs are not the answer for everything. If you need 24-bit resolution at low frequencies with built-in noise filtering, a sigma-delta converter is going to beat a SAR on performance and simplicity. If you need to sample at tens or hundreds of MSPS, a pipeline or flash ADC is more appropriate. SAR sits in a sweet spot for medium speed and medium resolution, typically up to a few MSPS and up to 18 bits or so. Beyond that the architecture starts to struggle because the DAC needs too many switches and capacitors, and the settling time becomes a problem. Another limitation: SAR converters have a sample-and-hold, but it is usually a passive one. That means the input impedance is capacitive and it changes during the conversion. If you are driving multiple channels on a multiplexed SAR ADC, you need to allow enough time between channel switches for the input capacitor to settle. I've seen designs that switched channels too quickly and got cross-talk between channels that looked like gain error. The fix was simply adding a small delay between channel changes, usually 10 to 20 microseconds depending on the source impedance and the capacitor size. It costs you sampling rate but it fixes the problem cleanly. The bottom line is that a Successive Approximation Analog To Digital Converter is a solid, predictable choice for most embedded measurement applications. It is not magical, it has real limitations, and it will punish you if you ignore the analog design details. Get the reference right, drive it from a low-impedance source, give it clean power and ground, and calibrate it if you need better performance than the spec sheet says. Everything else is refinement.
